I. Field of the Invention
This invention relates to the field of frequency dividers, and more specifically, programmable frequency dividers capable of a 50% duty cycle for odd and even integer divide ratios.
II. Background of the Invention
In order to provide greater flexibility in frequency planning, a competitive integrated circuit (IC)-based high frequency transceiver requires fully programmable frequency division. For example, in the receiver portion of the transceiver, a local oscillator (LO) frequency is typically a multiple of a certain reference frequency, and a programmable frequency divider is included in a phase locked loop (PLL) to generate the correct LO frequency. In the transmitter portion of the transceiver, a programmable frequency divider is typically included in the translational loop to generate the necessary radio (RF) or intermediate frequency (IF).
Conventional approaches employing counters or cascaded flip-flops may not be acceptable in every situation because they are incapable of producing an output having a 50% duty cycle, no matter what the integer divide ratio, or are incapable of doing so at odd integer divide ratios. FIG. 1A illustrates a clock signal, and FIG. 1B illustrates an output signal representing a division ratio of 3 obtained from a conventional frequency divider. As can be seen, the duty cycle of the signal, representing the fraction of a period the signal is in a high state, deviates substantially from 50%. A 50% duty cycle in the output signal is preferred because such signals lack even harmonics. Even harmonics in the output signal are sought to be avoided because they may cause spurious effects in many high frequency applications. For example, in integrated circuits, the introduction of even harmonics defeats the purpose of using purely differential mode signals.
Consequently, there is a need for a programmable frequency divider that is capable of producing a 50% duty cycle in the output signal at all integer divide ratios, both odd and even.
In accordance with the purpose of the invention as broadly described herein, there is provided a frequency divider configured to provide an output signal having a period equal to a period of a clock signal multiplied by a division ratio, the frequency divider comprising a plurality of edge triggered storage elements arranged in at least one loop, each of the elements having a state, and a clock input, wherein the state of each storage element is determined responsive to a transition of the clock input, the state, or the inverse thereof, of one or more previous elements in the loop, a characteristic of the division ratio, and the previous state, or the inverse thereof, of the storage element, and the output signal is derived from the state, or the inverse thereof, of at least one of the elements in the loop. In one implementation, the division ratio N which is achieved is related to the number of storage elements F by the following equation:   F  =            N      +      P        2  
where P is 1 if the division ratio is odd, and 0 if the division ratio is even. Thus, for example, a division ratio of either 5 or 6 could be achieved with 3 storage elements.
In one embodiment, the loop is configured such that an odd number of loop inversions are present in the loop. In one implementation, the loop inversions are implemented through inverters. In another implementation, the loop inversions are implemented through suitable routing of differential mode lines or signals.
In one implementation, each of the storage elements is configured to normally trigger on a first edge of the clock signal, and to trigger on a second edge of the clock signal if the control signal is in a first predetermined state and the data output of the storage element is in a second predetermined state. In one implementation example, the first predetermined state of the control signal indicates that the division ratio is an odd integer, and the second predetermined state of the data output is a logical high. Thus, in this implementation example, each of the storage elements normally triggers on a first edge of the clock signal, and triggers on a second edge of the clock signal if the control signal indicates an odd integer division ratio and the data output of the storage element is high.
In a second embodiment, the number of storage elements which contributes to the frequency division function is determined responsive to the desired division ratio. This number may be less than the number of storage elements physically present. In this embodiment, a circuit, responsive to the desired division ratio, configures the loop with the number of storage elements which are necessary to achieve the desired division ratio.
In one implementation, the number F of storage elements needed to perform the frequency division operation is determined by the equation:   F  =            N      +      P        2  
where N is the desired division ratio, and P is 1 if the desired division ratio is odd, and 0 if the desired division ratio is even. Once F is determined, a series F of storage elements is selected from a physical sequence. A multiplexor forms the loop from these F elements. Any remaining storage elements in the sequence are unused.
In a third embodiment, a power saving feature is provided in which unused storage elements are placed in a power saving mode. In one implementation, each of the control and clock signal inputs to a storage element are configured as current mode signals in which a logical xe2x80x981xe2x80x99 is represented through a current flow in a direction towards ground, and a logical xe2x80x980xe2x80x99 is represented by the lack of such a current flow. Each of these current mode signals is configured with a transistor which is provided along the flow path of the current mode signal to ground. All of these transistors for a given storage element are turned off if the storage element is unused for a given application.
In one implementation of the invention, each storage element comprises a flip-flop coupled to a clock phase module which selectively alters the phase of the clock signal responsive to the state of the control signal and the data output of the flip-flop. In one example, each storage element is configured to normally trigger on a rising edge of the clock signal, and to trigger on the falling edge in the exceptional case. In this example, the clock phase module inverts the phase of the clock to the flip-flop if the control signal indicates that the division ratio is an odd integer, and the data output of the storage element is in a logical high state, but otherwise leaves the phase of the clock unchanged.
In one example application, the frequency divider of the invention is a component of a frequency synthesizer which in turn is a component of a transceiver. The transceiver, in turn, may be a component of a wireless communications device, including a mobile wireless communication device such as a mobile wireless handset. The device in turn may be included in a wireless communications system of the type in which a geographical area is divided into a plurality of cells, and a base station in included within each cell. The base station for a cell communicates with one or more mobile wireless devices within the cell through a wireless communications interface.
In another example application, the frequency divider of the invention is a component of a translation loop which forms the transmitter section of a transceiver. The transceiver, in turn, may be a component of a wireless communications device, including a mobile wireless communication device such as a mobile wireless handset. The device in turn may be included in a wireless communications system of the type in which a geographical area is divided into a plurality of cells, and a base station in included within each cell. The base station for a cell communicates with one or more mobile wireless devices within the cell through a wireless communications interface.
A related method of operation for a storage element in accordance with the subject invention comprises the steps of triggering upon a first edge of the clock signal if the desired division ratio N has a first predetermined characteristic or the data output of the storage element is in a first predetermined state, and triggering upon a second edge of the clock signal if the desired division ratio N has a second predetermined characteristic and the data output of the storage element is in a second predetermined state. In one implementation, the first predetermined characteristic of the division ratio is that it be an even integer, and the second predetermined characteristic of the division ratio is that it be an odd integer. In addition, in this implementation, the first predetermined state of the data output of the storage element is a logical low, and the second predetermined state of the data output of the storage element is a logical high. In one example, the first edge of the clock signal is a rising edge, and the second edge of the clock signal is a falling edge.
Other related embodiments, implementations, implementation examples, configurations, and methods are possible which are within the scope of the subject invention.